With the demand for higher levels of integration of semiconductor chips, such as silicon semiconductor chips, and the need for greater density in these circuits, the spacing between the gates of field effect transistors (FET) in forming local interconnects to the source and drain of the FET becomes more and more critical. This is specially the case with a microprocessor integrated circuit chip of which a large portion of the real estate of the chip is an SRAM. For increased performance of future microprocessor, the storage capacity of the SRAM must increase thereby requiring a larger portion of real estate of the microprocessor.
The use of local interconnect (LI), in particular with the damascene method, greatly enhances packing density since it generally has much tighter pitch than other global interconnect methods such as aluminum metallization. Further, damascene and other similar LI methods result in smaller transistor size by eliminating the tolerance space commonly used to prevent source/drain contacts from misaligning onto the field oxide regions. However, tolerance space between gates and/or resistors is still required and must be larger than the misalignment error of the lithographic tools used in forming the LI. If this tolerance space can be reduced or all together eliminated without shorting of the local interconnect opening to adjacent unrelated polysilicon gates or resistors, the packing efficiency can be further enhanced. One shortcoming of the damascene local interconnect method is its inability to route over unrelated conductors, such as a transistor gate, or unrelated resistors. A method that enables such capability will further enhance packing density.